1. Field of the Invention
It is related to an exposure mask, a manufacturing method of an electronic device, and a checking method of an exposure mask.
2. Description of the Related Art
In a manufacturing process of semiconductor devices such as LSIs, mask pattern formed on a reticle (an exposure mask) is projected with reduced size onto a semiconductor wafer by use of exposure system such as stepper in order to form fine device patterns.
Although mask patterns on a reticle is formed in accordance with device patterns of LSIs, the mask patterns cannot be projected on a semiconductor wafer in predetermined shapes when the mask patterns are deformed.
For this reason, after the reticle is manufactured, it is usually investigated whether the mask patterns are formed at a predetermined accuracy by optically checking inspection marks formed on a reticle.
FIG. 1 is an entire plan view of a reticle provided with the inspection mark according to a conventional example.
The reticle 1 includes four mask patterns 6, each corresponding to four chips, on a transparent substrate 2 such as quartz substrate. Additionally, a light blocking zone 3 is formed so as to surround these mask patterns 6, and a region inside the light blocking zone 3 becomes a shot region that is subjected to projection onto a semiconductor wafer by one time exposure. Note that the light blocking zone 3 is provided for the purpose of preventing a photoresist from being unnecessarily exposed to light that is originated with the outside of the light blocking zone 3.
Then, in a region outside of the light blocking zone 3, L-shaped inspection marks 5 are formed to check whether the abovementioned mask patterns 6 have been formed in designed positions, and cross alignment marks 4 are formed to align the reticle 1 with an exposure system.
Note that all of the abovementioned elements 3 to 6 are formed by patterning a light blocking film made of a chrome film or the like.
However, even though the inspection marks 5 is formed in an outside region of the light blocking zone 3 in the reticle 1 of abovementioned structure, such a phenomenon occurs that the inspection marks are diffracted and projected onto the semiconductor wafer at the time of exposure. Such a phenomenon is called illumination-based flare, and becomes one of factors generating a defect in device patterns of the semiconductor wafer.
Another idea for preventing such illumination-based flare is to form the inspection marks 5 inside the mask patterns 6.
However, because each of the inspection marks 5 has to be formed in a shape that is large to some extent in order to facilitate the checking, there occurs an inconvenience that sizes of the chips become larger as the inspection marks 5 are made larger.
Moreover, if the inspection marks 5 are formed inside the mask patterns 6, dummy patterns corresponding to the inspection marks 5 are inevitably formed on the semiconductor wafer, and a density in a distribution of the device patterns is disturbed by these dummy patterns.
FIGS. 2 to 5 are plan views each provided for describing conditions imposed on a distribution of device patterns such as metal wiring in semiconductor devices.
In an example of FIG. 2, device patterns 11 formed on a semiconductor wafer 10 are formed so that a density of a distribution thereof becomes uniform within a plane. Such a distribution is an ideal distribution of the device patterns 11.
In contrast to this example, in FIGS. 3 to 5, distributions of device patterns are sparse (FIG. 3), dense (FIG. 4), and has a pattern inserted which is different from the other device patterns 11 surrounding the pattern (FIG. 5) in regions A indicated by dotted lines. When the device patterns 11 are distributed with such a nonuniform density, the surface of an interlayer insulating film formed on these device patterns 11 has heights being low in the part where the distribution is sparse, and being high in the part where the distribution is concentrated, whereby a step is generated in the interlayer insulating film.
In order to suppress generation of such a step, it is necessary to make a density of the device patterns 11 within a plane as uniform as possible without forming the inspection marks 5 inside the mask patterns 6. Such a restriction is essential for a layer (a critical layer), such as a gate electrode that needs to be formed with fine work.
On the other hand, in Japanese Patent Application Laid-open Publication No. Hei5-341499, alignment marks are provided in a scribe region of a reticle to form marks on a semiconductor wafer for the purpose of alignment, and protective patterns are provided in portions of the scribe region which face these alignment marks. Portions onto which the alignment marks are projected in an initial exposure are blocked from light by the protective patterns in a subsequent exposure, whereby it is made possible to leave, on the semiconductor wafer, marks corresponding to the alignment marks.
However, if the marks are thus left in the scribe region, burrs are generated from the marks at the time of cutting out semiconductor chips by dicing, and there arises a problem that semiconductor chips to which these burrs are attached are defective.
Note that such alignment marks are also disclosed in Japanese Patent Application Laid-open Publication No. Hei3-018012.